Debugging Multiple Clock Domain Signals - 2020.2 English

Vivado Design Suite User Guide: Model-Based DSP Design Using System Generator (UG897)

Document ID
UG897
Release Date
2020-11-18
Version
2020.2 English

In System Generator, you can use cross probing between the signal in the Xilinx Waveform Viewer and the Simulink® diagram to aid the debugging process.

Figure 1. Source Clock Domain

To add a signal to the Waveform viewer, right-click the signal in the model and select Xilinx Add To Viewer. Simulating the design should launch the Waveform Viewer as shown below.

Figure 2. Waveform Viewer

All signals in same clock domain are colored similarly. In the figure above: src_domain/Slice/Out1 and dest_domain/Relational/Out1 are in different clock domains.