System Generator is a bit and cycle accurate modeling tool. You can verify the functionality of your designs by simulating in Simulink® . However, to ensure that your System Generator design will work correctly when it is implemented in your target Xilinx® device, these analysis tools have been integrated into System Generator:
- Timing Analysis
- To ensure that the HDL files generated by System Generator operate correctly in hardware, you must close timing. To help accelerate this process, timing analysis has been integrated into System Generator.
- Resource Analysis
- To ensure that the HDL files generated by System Generator will fit into your target device, you may need to analyze the resources being used. To help accelerate this process, resource analysis has been integrated into System Generator.
| Timing Analysis in System Generator | Presents an overview of timing analysis in System Generator. |
| Describes how to perform timing analysis on your model. | |
| Describes how you can cross probe from a row in the Timing Analyzer table to the Simulink model, highlighting the corresponding System Generator blocks in the path. | |
| Describes how to re-launch the Timing Analyzer table on pre-existing Timing Analysis results. | |
| Describes methods to help you discover the source of timing violations in your design. | |
| Resource Analysis in System Generator | Presents an overview of resource analysis in System Generator. |
| Describes how to perform resource analysis on your model. | |
| Describes how you can cross probe from a row in the Resource Analyzer table to the Simulink model, highlighting the corresponding block or subsystem in the design. | |
| Describes how to re-launch the Resource Analyzer table on pre-existing Resource Analysis results. | |
| Describes methods to help you use the Resource Analyzer to optimize resource utilization in the design. |