Performing Timing Analysis - 2020.2 English

Timing analysis can be invoked whenever you generate any of the following compilation targets:

• IP catalog
• Hardware Co-Simulation
• Synthesized Checkpoint
• HDL Netlist

To perform timing analysis in System Generator:

1. Double-click the System Generator token in the Simulink model.
2. Enter the following in the System Generator token dialog box:
   • In the Compilation tab, specify a Target Directory.
   • In the Clocking tab, set the Perform Analysis field to Post Synthesis or Post Implementation based on the runtime vs. accuracy tradeoff.
   • In the Clocking tab, set the Analyzer Type field to Timing.
   Figure 1. Performing Timing Analysis
3. In the System Generator token dialog box, click Generate.

   When you generate, the following occurs:

   1. System Generator generates the required files for the selected compilation target. For timing analysis System Generator invokes Vivado in the background for the design project, and passes design timing constraints to Vivado.
   2. Depending on your selection for Perform Analysis (Post Synthesis or Post Implementation), the design runs in Vivado through synthesis or through implementation.
   3. After the Vivado tools run is completed, timing paths information is collected and saved in a specific file format from the Vivado timing database. At the end of the timing paths data collection the Vivado project is closed and control is passed to the MATLAB® /System Generator process.
   4. System Generator processes the timing information and displays a Timing Analyzer table with timing paths information (see below).
   Figure 2. Timing Analyzer Table
   
   

   In the timing analyzer table:

   • Only unique paths from the Simulink model are reported.
   • The 50 paths with the lowest Slack values are displayed with the worst Slack at the top, and increasing Slack below.
   • Paths with timing violations have a negative Slack and display in red.
   • The display order can be sorted for any column’s values by clicking the column head.
   • If you want to hide a column in the table, right-click any column head in the table and deselect the column to hide in the list that appears.
     Figure 3. Hide/Show Dialog
     

     

     
     
   • For a design with multiple clock cycle constraints, the Timing Analyzer can identify multicycle path constraints, and show them in the Path Constraints column. In that case, the Source Clock, and Destination Clock columns display clock enable signals to reflect different sampling rates.
     Figure 4. Clock Enable Signals
     
     
   • You can cross probe from the table to the Simulink model by selecting a path in the table, which will highlight the corresponding System Generator blocks in the Simulink model. See Cross Probing from the Timing Analysis Results to the Model.