The "Clock Enables" Multirate Implementation - 2020.2 English

Vivado Design Suite User Guide: Model-Based DSP Design Using System Generator (UG897)

Document ID
UG897
Release Date
2020-11-18
Version
2020.2 English

Clock and clock enables appear in pairs throughout the HDL. Typical clock names are clk_1, clk_2, and clk_3, and the names of the companion clock enables are ce_1, ce_2, and ce_3 respectively. The name tells the rate for the clock/clock enable pair; logic driven by clk_1 and ce_1 runs at the system (i.e., fastest) rate, while logic driven by (say) clk_2 and ce_2 runs at half the system rate. Clocks and clock enables are not driven in the entity or module named <design> or any subsidiary entities; instead, they are exposed as top-level input ports

The names of the clocks and clock enables in System Generator HDL suggest that clocking is completely general, but this is not the case. To illustrate this, assume a design has clocks named clk_1 and clk_2, and companion clock enables named ce_1 and ce_2 respectively. You might expect that working hardware could be produced if the ce_1 and ce_2 signals were tied high, and clk_2 were driven by a clock signal whose rate is half that of clk_1. For most System Generator designs this does not work. Instead, clk_1 and clk_2 must be driven by the same clock, ce_1 must be tied high, and ce_2 must vary at a rate half that of clk_1 and clk_2.