CSV File‌ - 2023.2 English

Vivado Design Suite User Guide: I/O and Clock Planning (UG899)

Document ID
UG899
Release Date
2023-10-18
Version
2023.2 English

A CSV file is a standard file format used by FPGA and board designers to exchange information about device pins and pinout. For more information, see Importing a CSV File and Exporting I/O Pin and Package Data.

Following are descriptions of the CSV columns. For more information on each property, see the Vivado Design Suite Properties Reference Guide (UG912).

I/O Bank
Specifies the I/O Bank in which the pin is located. The tool fills in this field for all pins in the device. Values are a number or blank. This is not required in the input CSV file.
Pin Number
Specifies the name (or location) of the package pin. The tool writes this out for all pins in the device. This is not required in the input file. If used for input, it is used to define placement. Values are legal pins in the device.
Site
Specifies an alternate part name for the package pin. This field is specified by the tool and is unused if specified in the input CSV file.
Note: Prior to 2016.1, this column was called IOB Alias.
Site Type
Specifies the pin name from the device data sheet. This field is specified by the tool and is unused if specified in the input CSV file.
Min/Max Trace Delay (ps)
Specifies the delay between the pad site of the die and the ball on the package in picoseconds. This is specified by the tool to help the board engineer match trace delays. The Trace Delay fields are in the output file only. They are not expected in the input file.
Trace Length (um)
Specifies the length of the internal trace between the package pin and the die pad.
Note: This is not published for most devices. Use trace delay instead and see Package Trace Length for more information.
Prohibit
Specifies a prohibit site. Certain sites can be prohibited to prevent user I/O from being added to the site. For example, sites can be prohibited to:
  • Prohibit ease board layout issues.
  • Reduce crosstalk between signals.
  • Ensure that a pinout works between multiple FPGAs in the same package.
    Note: In the XDC file, this is represented by a PROHIBIT property.
Interface
An optional user-specified grouping for an arbitrary set of user I/O. For example, this field provides a means to specify a relationship for the data, address, and enable signals for a memory interface. Values are a text string or blank.
Signal Name
The name of the user I/O in the FPGA design. Values are a string or blank for an unassigned Package Pin.
Direction
The direction of the signal. Values are IN, OUT, INOUT, or blank when a user I/O is not assigned to the site.
DiffPair Type
This value instructs the software about which pin is the N side of a differential pair, and which pin is the P side. This is used for differential signals only. The tool uses this column instead of a naming convention to determine which pin is the N side of the pair, and which pin is the P side. Values are P, N, or blank when a user I/O is not assigned to the site.
DiffPair Signal
Specifies the name of the other pin in the differential pair. Values are the name of the user I/O or blank when unused.
IO Standard
Specifies the I/O standard for a specific user I/O. When this field is blank for a user I/O, the tool uses the appropriate device defaults. Values are a legal I/O standard for the user I/O in the device or blank.
Drive
Drive strength of the I/O standard for a specific user I/O. Not all I/O standards accept a drive strength. If this field is blank, the tool uses the default. Values are a number or blank.
Slew Rate
Specifies the I/O standard slew rate for a specific user I/O. Not all I/O standards accept a slew rate. If this field is blank, the tool uses the default. Values are FAST, MEDIUM (AMD UltraScale™ Architecture only), and SLOW.
OUTPUT_IMPEDANCE
(Supported by all architectures after 7 series) Specifies the driver impedance for HSTL, SSTL, HSUL, LVDCI, HSLVDCI, and POD drivers to match the characteristic impedance of the driven line. The OUTPUT_IMPEDANCE attribute defines the value of source termination at the driver for both DCI and non-DCI versions of the supported standards.
PRE_EMPHASIS
(Supported by all architectures after 7 series) Allows pre-emphasis for certain I/O standards to improve signal integrity of high-frequency signals by reducing intersymbol interference and minimizing the effects of transmission line losses.
LVDS_PRE_EMPHASIS
(Supported by all architectures after 7 series) Allows pre-emphasis for LVDS I/O standards to improve signal integrity of high-frequency signals by reducing intersymbol interference and minimizing the effects of transmission line losses.
Pull Type
Specifies the pull type for the selected port. When using 3-state output (OBUFT) or bidirectional (IOBUF) buffers, the output can have a weak pull-up resistor, a weak pull-down resistor, or a weak “keeper” circuit. For input (IBUF) buffers, the input can have either a weak pull-up resistor or a weak pull-down resistor.
IN_TERM
(7 series devices only) Defines the optional IN_TERM or OUT_TERM driver impedance properties. This is most commonly left blank but is supported for production devices. Using this terminal definition overrides the SLEW and DRIVE STRENGTH properties and is not supported in SSN calculations.
DQS_BIAS
(Supported by all architectures after 7 series) Defines an optional DC bias at the inputs of certain pseudo-differential and true differential IO standards.
DIFF_TERM
Turns the built-in differential termination on or off.
OFFCHIP_TERM
Specifies the external board level termination of the I/O. This is used for SSN calculations. If the field is left blank, the tool uses the expected terminations in the SSN calculations and shows this expected termination by default in the SSN report and I/O Ports table.
Note: For information on the expected terminations as well as the corresponding shortened names that display in the tool, see the SelectIO™ Resources User Guide for your device.
  • 7 Series FPGAs SelectIO Resources User Guide (UG471)
  • UltraScale Architecture SelectIO Resources User Guide (UG571)
Board Signal
Specifies the name of the signal coming into the I/O from the board-level design.
Board Voltage
Specifies the voltage level of the signal coming into the I/O from the board-level design.
ODT
(Supported by all architectures after 7 series) Reports the design's optional on-chip Termination.
Important: The columns listed above are read in as constraint values and any additional columns are retained as user defined columns in the Package Pins window. Additional constraints for I/O should be imported through XDC.