Clock Planning‌‌ - 2023.2 English

Vivado Design Suite User Guide: I/O and Clock Planning (UG899)

Document ID
UG899
Release Date
2023-10-18
Version
2023.2 English

In clock planning, you determine how to use various clock resources on the AMD device to distribute the clocks across the device. An AMD device is subdivided into columns and rows of clock regions. A clock region contains CLBs, DSP slices, block RAMs, interconnect, and associated clocking resources. The size and contents of a clock region vary by device type. For example, in AMD UltraScale™ devices, the clock region spans 60 CLBs, 24 DSP slices, and 12 block RAMs with a horizontal clock spine (HCS) at its center. In 7 series devices, the clock region spans 50 CLBs and 1 I/O bank, which includes 50 I/Os, with a horizontal clock row (HROW) at its center.

A system clock, or board clock, is a primary clock that enters the design through an input port or a gigabit transceiver output pin. Each I/O bank contains clock-capable input pins to bring system clocks onto the device and into clock routing resources. In conjunction with dedicated clock buffers, the clock-capable input pins bring system clocks onto:

  • Global clock lines
  • I/O clocks lines within the same I/O bank and adjacent I/O banks
  • Regional clock lines within the same clock region and vertically adjacent clock regions
  • Clock management tiles (CMTs)
    Note: You can define the primary clock using the create_clock Tcl command. For more information on the create_clock command, see the Vivado Design Suite Tcl Command Reference Guide (UG835).
    When working with a synthesized or implemented design, you can manually place global and regional clock-related logic, such as BUFGCTRLs, MMCMs, BUFRs, and IDELAYCTRLs, using the Clock Resources window. You can also manually place clock logic in the Device window. Appropriate logic sites are displayed in the Device window for all device-specific resources. For more information on clock planning, see the one of the following Clocking Resources User Guide, depending on your device.
    • 7 Series FPGAs Clocking Resources User Guide (UG472)
    • UltraScale Architecture Clocking Resources User Guide (UG572)
    Tip: The AMD Vivado™ tools handle clock planning automatically during implementation. You can then use interactive clock planning to manually address clocking issues.