GT components are updated from Common/Channel to a GT_QUAD granularity for AMD Versal™ adaptive SoC. To enable some of the GT sharing use cases, GT wizard flows are modified to use the Vivado IP integrator. Use the Vivado IP integrator to build system designs that use single or multiple GT_QUADs. The design entry for custom IP that connects to GT_QUADs is through the Bridge IP, which instantiates, configures, and connects single or multiple GT Quad-based IP through Block Automation. Because GT_QUADs can be shared between multiple IPs, GT_QUAD and REFCLK locations are not assigned in IP integrator.
The Hard Block Planner provides an intuitive user interface to assign GT_QUAD and REFCLK locations. The Hard Block Planner window groups GT_QUADs under Hard-IPs such as PCIe® and DCMAC. Furthermore, it provides an easy to use mechanism to assign GT_QUADs using the device sites. The Hard Block Planner provides visual feedback in the Device window for location of the REFCLK pins, the GT_QUADs and the Hard-IP blocks. It also lists the soft IPs in the design under a separate drop down menu alongside the hard IPs (highlighted in green) to facilitate the planning of its associated GT blocks. List of supported hard IPs include DCMAC, MRMAC, PCIe® , CPM, and ILKN. Once you open a synthesized design, it reads and processes netlist objects and collects all hard-IPs available in a design. This planner allows you to cross-probe the location in Device window view for changing or assigning the Site. The Hard Block Planner option in the Windows menu appears only once you open a synthesized design or implemented design. Hard Block Planner window has 3 buttons on top (highlighted in red). The first button on the left marks all hard blocks in blue, all associated GTs in red and the REFCLK sources in green. The button in the middle does the same for a selected IP group. The last button on the right removes the marks from all items to clear up the device view. These buttons can be used to quickly glance the relative placement of IPs and their associated GT in Device View.
Figure 1. Hard Block Planning for Versal Adaptive SoC