I/O and Clock Planning Using the Platform Board Flow‌ - 2023.2 English

Vivado Design Suite User Guide: I/O and Clock Planning (UG899)

Document ID
UG899
Release Date
2023-10-18
Version
2023.2 English

In the Vivado Design Suite, you can select pre-configured targeted design platform boards as the target for a design. Information about each platform board, including the target AMD device or devices, additional board components, signal interfaces, I/O configurations, and various preferred IP configuration options are stored in a Board Interface file. The Vivado Design Suite provides a set of Board Interface files for predefined boards, and you can also define your own targeted platform boards for use in the Vivado tools. For more information on the platform board flow, see section The Vivado Design Suit Board Flow in the Vivado Design Suite User Guide: System-Level Design Entry (UG895).

I/O requirements can change based on the IP configurations and signal interfaces used when you customize an IP. When working with IP from the Vivado IP catalog in the platform board flow, you can automatically define the package pin assignment and all of the I/O-related constraints, such as IOSTANDARD, SLEW, and DRIVE.

In addition, various Vivado Design Suite Tcl commands let you access information in the Board Interface file while working in an I/O planning project, an RTL design project, or a post-synthesis netlist project. You can use the information from the Board Interface file to group ports and define interfaces or to define the required ports for a specific FPGA configuration. For more information, see Automatically Inferring I/O Port Interfaces.