I/O and Clock Planning for IP with I/O Ports‌ - 2023.2 English

Vivado Design Suite User Guide: I/O and Clock Planning (UG899)

Document ID
UG899
Release Date
2023-10-18
Version
2023.2 English

Certain types of IP, such as Memory, GT, PCIe, and Ethernet interfaces have I/O ports associated with them. You must properly configure this IP using the IP capabilities in the Vivado Design Suite prior to beginning the I/O planning process. Because these interfaces are usually the most timing critical, use this IP as the starting point when considering the device pin assignments. In addition, use an RTL or synthesized design for the I/O pin planning process when using this IP.

Define the I/O physical pin assignments for the GT, PCIe IP, Ethernet, and Memory IP as part of IP customization when the core is added to the design. To change the I/O assignments, re-customize the IP in the design. For information on working with and customizing IP, see the Vivado Design Suite User Guide: Designing with IP (UG896). For UltraScale architecture Memory IP, the I/O assignment is integrated into the standard I/O planning flow and does not require Memory IP customization. For more information, see I/O Planning for UltraScale Architecture Memory IP.