I/O and clock planning is the process of defining and analyzing the connectivity between the FPGA/adaptive SoC and the printed circuit board (PCB) and assigning the various interconnect signals to physical pins of the device. This process includes PCB designers, FPGA designers, and system designers with the following concerns and requirements:
- Streamlining the critical signal connectivity to shorten signal lengths and avoid signal crossings.
- Maintaining the integrity of high speed signals on and off of the device.
- Selecting an I/O configuration that might work with alternate devices.
- Determining power and ground signal availability on the PCB.
- Establishing PCB requirements for proper decoupling.
- Identifying device programming and debugging considerations.
Often, designers are hindered by a non-optimal pinout that causes further delays when they trying to meet timing and signal integrity requirements. By considering the data flow from the PCB to the FPGA/adaptive SoC die, you can achieve optimal pinout configurations quickly, thus reducing internal and external trace lengths as well as routing congestion. This chapter provides an overview of the I/O and clock planning process using the graphical user interface (GUI) known as the AMD Vivado™ Integrated Design Environment (IDE).