Xilinx® documentation is organized around a set of standard design processes to help you find relevant content for your current development task. All Versal® ACAP design process Design Hubs and the Design Flow Assistant materials can be found on the Xilinx.com website. This document covers the following design processes:
- System and Solution Planning
- Identifying the components, performance, I/O, and data transfer requirements at a system level. Includes application mapping for the solution to PS, PL, and AI Engine.
The following table summarizes various interface speed options available in each architecture for easy document navigation. Note that the bit-rates mentioned in the table are based on hardware characterization using LVDS in speed grade -3 devices.
|Device Architecture||Additional Considerations||Relevant Links|
HRIO (Low Speed I/O)
Component Mode (Low Speed
Native Mode (High Speed I/O)
I/O Logic (Low Speed I/O)
XPIO (High Speed I/O)