You can perform I/O planning in an elaborated RTL project. With this method, you use an RTL design, which optionally includes IP cores from the Vivado IP catalog or block designs from the Vivado IP integrator. Using the IP catalog, you can customize IP, customize clocking components using the Clocking wizard, and configure SelectIO™ interface resources using the SelectIO Interface wizard. In an elaborated design, the Vivado tools provide basic DRCs to check port assignments, I/O standards, clock resources, and other design details. You can do initial I/O and clock planning with the elaborated design and export device and I/O port assignments for use in PCB schematic symbol generation or save the constraints in an XDC file for use during synthesis or implementation.
Note: For information on creating an RTL project and opening the elaborated design, see section "RTL Projects" in the Vivado Design Suite User Guide: System-Level Design Entry (UG895).