Setting Device Constraints‌‌ - 2023.2 English

Vivado Design Suite User Guide: I/O and Clock Planning (UG899)

Document ID
UG899
Release Date
2023-10-18
Version
2023.2 English

In the Device Constraints window (shown in the following figure), you can set constraints, including DCI_ CASCADE and INTERNAL_VREF. AMD devices have configurable SelectIO™ interface drivers and receivers that support many standard interfaces. This feature set includes programmable control of output strength and slew rate, on-chip termination using digitally-controlled impedance (DCI), and the ability to internally generate a reference voltage (INTERNAL_VREF).

Depending on the I/O standard, AMD DCI can either control the output impedance of a driver or add a parallel termination to the driver, receiver, or both, with the goal of accurately matching the characteristic impedance of a transmission line. DCI actively adjusts the impedance inside an I/O bank to calibrate to external precision reference resistors placed on the VRN and VRP pins. This compensates for changes in I/O impedance due to process variation or variations of temperature and supply voltage. DCI uses two multi-purpose reference pins in each I/O bank to control the impedance of the driver or the parallel-termination value for all of the I/Os in the bank.

Single-ended I/O standards with a differential input buffer require a VREF. When a VREF is required within an I/O bank, use the following pins for the bank as VREF supply inputs:

  • For UltraScale architecture-based devices, use the dedicated VREF pin
  • For 7 series devices, use the two multifunction VREF pins

Alternatively, you can generate an internal VREF using the INTERNAL_VREF constraint. Using internal reference voltages can remove the need to provide a particular VREF supply rail on the PCB and can free multipurpose VREF pins in a given I/O bank for other I/O port assignments. Each I/O bank has one VREF plane, and each bank can have the optional INTERNAL_VREF set to a single voltage level for the entire bank.

For more information, see the 7 Series FPGAs SelectIO Resources User Guide (UG471) or the UltraScale Architecture SelectIO Resources User Guide (UG571) depending on your device.

Figure 1. Device Constraints Window