Setting the Configuration Bank Voltage Select Pin‌ - 2023.2 English

Vivado Design Suite User Guide: I/O and Clock Planning (UG899)

Document ID
UG899
Release Date
2023-10-18
Version
2023.2 English

The configuration bank voltage select (CFGBVS) logic input pin is referenced between VCCO_0 and GND. The CFGBVS pin must be set to High or Low to determine the I/O voltage support for the pins in bank 0. In the Vivado tools, you can use Tcl commands to set the CFGBVS tie off information to either VCCO or GND. You can set the configuration voltage, or VCCO_0 voltage, to 1.5, 1.8, 2.5, or 3.3. Based on these settings, DRCs are run on Bank 0, 14, and 15 for 7 series devices. For UltraScale devices, DRCs are run on Bank 0 and 65. These values are also used when exporting IBIS models.

Following is an example:

set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]

By default, the CFGBVS property is empty. The Vivado tools check whether the CFGBVS property is set to VCCO or GND. If the CFGBVS property has a value, the Vivado tools check for a CONFIG_MODE property. DRCs are issued based on IOSTANDARD and CONFIG_VOLTAGE settings for the bank.

When you export to a CSV file, the Vivado tools provide VCCO tie off information for the relevant banks (for 7 series devices: banks 0, 14, and 15; for AMD UltraScale™ architecture-based devices: banks 0 and 65) based on the setting for the CONFIG_MODE property. For example, if you use JTAG/Boundary Scan, CFGBVS is GND, and CONFIG_VOLTAGE is 3.3, the tools issue the critical warning: DRC CFGBVS-4. This indicates that the CONFIG_VOLTAGE is set to and must instead be set to VCCO, which has a value of 1.8. For AMD UltraScale+™ devices, you cannot manually set CFGBVS or CONFIG_VOLTAGE. By default, CFGBVS is set to GND and CONFIG_VOLTAGE is set to 1.8 V.

Note: For more information on the CFGBVS pin, see one of the following, depending on your device:
  • 7 Series FPGAs Configuration User Guide (UG470)
  • UltraScale Architecture Configuration User Guide (UG570)
  • Zynq UltraScale+ Device Technical Reference Manual (UG1085)