The AMD Vivado™ Design Suite has the following differences between the I/O assignment and implementation process for UltraScale architecture Memory IP:
- Consolidated Memory IP I/O planning with the rest of the design in the main Vivado IDE I/O Planning view layout, which enables pin planning with the design RTL or after synthesizing the design.
- PHY implementation of the IP now performed after synthesis as a part of the
opt_designcommand, which enables netlist based I/O planning.
- Physical block (Pblock) that contains the IP is now automatically generated as
a part of the
opt_designcommand and is transient and invisible to users.