In a mixed language design, you can instantiate a Verilog/SV module in a VHDL architecture or a VHDL component in a Verilog/SV module as described in the following subsections.
To ensure that you are correctly matching port types, review the Port Mapping and Supported Port Types.
Instantiating a Verilog Module in a VHDL Design Unit
- Declare a VHDL component with the same name and in the same case as the Verilog
module that you want to instantiate. For example:
COMPONENT MY_VHDL_UNIT PORT ( Q : out STD_ULOGIC; D : in STD_ULOGIC; C : in STD_ULOGIC ); END COMPONENT;
- Use named or positional association to instantiate the Verilog module. For
UUT : MY_VHDL_UNIT PORT MAP( Q => O, D => I, C => CLK);
Instantiating a VHDL Component in a Verilog/SV Design Unit
To instantiate a VHDL component in a Verilog/SV design unit, instantiate the VHDL component as if it were a Verilog/SV module.
module testbench ; wire in, clk; wire out; FD FD1( .Q(Q_OUT), .C(CLK); .D(A); );