References - 2023.2 English

These documents provide supplemental material useful with this guide:

1. Vivado Design Suite User Guide: Release Notes, Installation, and Licensing (UG973)
2. Vivado Design Suite User Guide: System-Level Design Entry (UG895)
3. Vivado Design Suite User Guide: Designing with IP (UG896)
4. Vivado Design Suite User Guide: Using the Vivado IDE (UG893)
5. Vivado Design Suite User Guide: Using Tcl Scripting (UG894)
6. Vivado Design Suite 7 Series FPGA and Zynq-7000 SoC Libraries Guide (UG953)
7. Vivado Design Suite Tcl Command Reference Guide (UG835)
8. Vivado Design Suite User Guide: Power Analysis and Optimization (UG907)
9. Vivado Design Suite User Guide: Using Constraints (UG903)
10. Vivado Design Suite Tutorial: Logic Simulation (UG937)
11. Vivado Design Suite User Guide: Design Flows Overview (UG892)
12. Vivado Design Suite Properties Reference Guide (UG912)
13. Vivado Design Suite User Guide: Synthesis (UG901)
14. Writing Efficient Test Benches (XAPP199)
15. IEEE Standard VHDL Language Reference Manual (IEEE-STD-1076-1993)
16. IEEE Standard Verilog Hardware Description Language(IEEE-STD-1364-2001)
17. IEEE Standard for SystemVerilog--Unified Hardware Design, Specification, and Verification Language (IEEE-STD-1800-2009)
18. Standard Delay Format Specification (SDF) (IEEE-STD-1497-2004)
19. Recommended Practice for Encryption and Management of Electronic Design Intellectual Property (IP) (IEEE-STD-P1735)