At post-synthesis and post-implementation, you can run a functional or a Verilog timing simulation. The following figure illustrates the post-synthesis and post-implementation simulation process:
The following is an example of running a post-synthesis functional simulation from the command line:
synth_design -top top -part xc7k70tfbg676-2
open_run synth_1 -name netlist_1
write_verilog -mode funcsim test_synth.v
launch_simulation -mode post-synthesis
write_sdf command after the
write_verilog command, and the appropriate annotate command is needed for elaboration and simulation.