Running Simulation Using Third Party Simulators with Vivado IDE - 2023.2 English

Vivado Design Suite User Guide: Logic Simulation (UG900)

Document ID
UG900
Release Date
2023-10-18
Version
2023.2 English
Important: Confirm the compiled library location (the path at which compile_simlib was invoked or the one you specified with the -directory option) before running a third-party simulation.

From the Vivado IDE, you can compile, elaborate, and simulate the design based on the simulation settings and launch the simulator in a separate window.

When you run a simulation prior to synthesizing the design, the simulator runs a behavioral simulation. Following each successful design step (synthesis and implementation), the option to run a functional or timing simulation becomes available. You can initiate a simulation run from the Flow Navigator or by typing in a Tcl command.

From the Flow Navigator, click Run Simulation, and select the type of simulation you want to run, as shown in the following figure:

Figure 1. Types of Simulation

To use the corresponding Tcl command, type: launch_simulation.

Tip: This command provides a -scripts_only option that can be used to write a DO or SH file, depending on the target simulator. Use the DO or SH file to run simulations outside the IDE.
Note: If you are running the VCS simulator outside of Vivado, make sure to use -full64 switch. Otherwise, the simulator does not run if the design contains an AMD IP.
Important: Use the following command to run the 32-bit Simulator: set_property 32bit 1 [current_fileset -simset]
Note: AMD Verification IP (VIP) uses SystemVerilog construct. If you are using any IP that instantiates VIP, make sure that your simulator supports SystemVerilog.