This chapter describes the command line compilation and simulation process.
Vivado supports an integrated simulation flow where the tool can launch Vivado simulator, or a third party simulator from the IDE. However, many users also want to run simulation in batch or scripted mode in their verification environment, which might include system-level simulation or advanced verification such as UVM. The Vivado Design Suite supports batch or scripted simulation in the Vivado simulator.
This chapter describes a process to gather the needed design files, generate simulation scripts for your target simulator, and run the simulation in batch mode. The simulation scripts can be generated for a top-level HDL design, for hierarchical modules, managed IP projects, or block designs from Vivado IP integrator. Batch simulation is supported in both project and non-project script-based flow.