The UNIMACRO library is used during the functional simulation and contains macro descriptions for selected device primitives.
VHDL UNIMACRO Library
To use these primitives, place the following two lines at the beginning of each file:
Verilog UNIMACRO Library
In Verilog, the individual library modules are specified in separate HDL files. This
-y library specification switch to search the specified
directory for all components and automatically expand the library.
The Verilog UNIMACRO library does not need to be specified in the HDL file prior to using the modules as is required in VHDL. To use the library module, specify the module name using all uppercase letters. You must also compile and map the library; the method you use depends on the simulator you choose.