Understanding the Simulator Language Option - 2023.1 English

Vivado Design Suite User Guide: Logic Simulation (UG900)

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2023.1 English

Most AMD IP deliver behavioral simulation models for a single language only, effectively disabling simulation for language-locked simulators if you are not licensed for the appropriate language. The simulator_language property ensures that an IP delivers a simulation model for any given language. For example, if you are using a single language simulator, you set the simulator_language property to match the language of the simulator.

The Vivado Design Suite ensures the availability of a simulation model by using the available synthesis files of an IP to generate a language-specific structural simulation model on demand. For cases in which a behavioral model is missing or does not match the licensed simulation language, the Vivado tools automatically generate a structural simulation model to enable simulation. Otherwise, the existing behavioral simulation model for the IP is used. If no synthesis or simulation files exist, simulation is not supported.

Note: The simulator_language property cannot deliver a language-specific simulation netlist file if the generated Synthesized checkpoint (.dcp) is disabled.
  1. In the Flow Navigator, click IP Catalog to open the IP catalog.
  2. Right-click the appropriate IP and select Customize IP from the popup menu.
  3. In the Customize IP dialog box, click OK.

The Generate Output Products dialog box (shown in the following figure) opens.

Figure 1. Generate Output Products Dialog Box

The following table illustrates the function of the simulator_language property.

Table 1. Function of simulator_language Property
IP Delivered Simulation Model simulator_language Value Simulation Model Used
IP delivers VHDL and Verilog behavioral models Mixed Behavioral model (target_language)
Verilog Verilog behavioral model
VHDL VHDL behavioral model
IP delivers Verilog behavioral model only Mixed Verilog behavioral model
Verilog Verilog behavioral model
VHDL VHDL simulation netlist generated from DCP
IP delivers VHDL behavioral model only Mixed VHDL behavioral model
Verilog Verilog simulation netlist generated from DCP
VHDL VHDL behavioral model
IP delivers no behavioral models Mixed, Verilog, VHDL Netlist generated from DCP (target_language)
  1. Where available, behavioral simulation models always take precedence over structural simulation models. The Vivado tools select behavioral or structural models automatically, based on model availability. It is not possible to override the automated selection.
  2. Use the target_language property when either language can be used for simulation Tcl: set_property target_language VHDL [current_project]
  3. Setting VHDL as a target language for AMD Versalâ„¢ devices is not yet supported. This will result in an error in simulation.