When a Verilog design instantiates a component, the
xelab command treats the component name as a Verilog unit and searches for a Verilog module in the user-specified list of unified logical libraries in the user-specified order.
- If found,
xelabbinds the unit and the search stops.
- If the case-sensitive search is not successful,
xelabperforms a case-insensitive search for a VHDL design unit name constructed as an extended identifier in the user-specified list and order of unified logical libraries, selects the first one matching name, then stops the search.
xelabfinds a unique binding for any one library, it selects that name and stops the search.Note: For a mixed language design, the port names used in a named association to a VHDL entity instantiated by a Verilog module are always treated as case insensitive. Also, you cannot use a
defparamstatement to modify a VHDL generic. See Using Mixed Language Simulation, for more information.Important: Connecting a whole VHDL record object to a Verilog object is unsupported.