Create a test bench for a design unit instance. This command creates a functional system Verilog-based test bench for the scoped hierarchical instance. The test bench contains port/signal specification, parameter declaration, stimuli vector include file and module instantiation of the selected instance as a design under test (DUT). This command allows you to add the test bench to an existing or a new simulation fileset from which the simulation can be launched.
|Specify the name of the test bench module name. The default name is test bench.
|Specify simulation fileset name to which the test bench needs to be added. If this switch is not specified, then the command adds a test bench to the current active simulation fileset.
|Set the generated test bench module at the top in the simulation fileset where the test bench is added.
|Specifies simulation mode. Allowed values are behavioral, post-synthesis, or post-implementation. The default is behavioral.
|Specifies simulation type. Allowed values are functional or timing (not applicable for behavioral mode).
|Overwrite existing test bench file.
|Execute the command quietly, returning no messages from the command.
The command also returns TCL_OK regardless of any errors encountered
Note: Any errors encountered on the command line while launching the command are returned. Only errors occurring inside the command are trapped.
|Temporarily override any message limits and return all messages from
Note: Message limits can be defined with the
The following example command creates a test bench for the fifo module and adds
it to the
sub_design_fifo simulation fileset:
create_testbench -name fifo -add_to_simset sub_design_fifo
The following example command generates a VCD file for /top/DUT/fifo/buf_1 instance of type buf module, record
the waveform activity in the VCD file for 2000 ns, create a test bench with module named
tb, add the test bench to the
fileset and set tb as top module in this fileset:
create_testbench -name tb -add_to_simset test_buffer -set_as_top