ASYNC_REG VHDL Examples - 2023.2 English

Vivado Design Suite User Guide: Synthesis (UG901)

Document ID
UG901
Release Date
2023-11-01
Version
2023.2 English
attribute ASYNC_REG : string;
attribute ASYNC_REG of sync_regs : signal is "TRUE";
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of sync_regs : signal is TRUE;