BLACK_BOX Verilog Example - 2023.2 English

Vivado Design Suite User Guide: Synthesis (UG901)

Document ID
UG901
Release Date
2023-11-01
Version
2023.2 English
(* black_box *) module test(in1, in2, clk, out1);
Important: In the Verilog example, no value is needed. The presence of the attribute creates the black box.