Binding - 2023.2 English

Vivado synthesis performs binding during elaboration. During binding, the following actions occur:

1. Vivado synthesis searches for a Verilog module with the same name as the instantiated module with a user-specified list of unified logical libraries and with a user-specified order.
2. Vivado synthesis ignores any architecture name specified in the module instantiation.
3. If Vivado synthesis finds the Verilog module, synthesis binds the name.
4. If Vivado synthesis does not find the Verilog module, it treats the Verilog module as a VHDL entity, and searches for the first VHDL entity matching the name using a case-sensitive search for a VHDL entity in the user-specified list of unified logical libraries or the user-specified order. This assumes that a VHDL design unit is stored with an extended identifier.