Blocks - 2023.2 English

Vivado synthesis supports some block statements, as follows:

• Block statements group statements together. They are designated by begin and end keywords. Block statements execute the statements in the order listed within the block.
• Vivado synthesis supports sequential blocks only.
• Vivado synthesis does not support parallel blocks.
• All procedural statements occur in blocks that are defined inside modules.
• The two kinds of procedural blocks are initial block and always block
• Verilog uses begin and end keywords within each block to enclose the statements. Because initial blocks are ignored during synthesis, only always blocks are described.
• always blocks usually take the following format. Each statement is a procedural assignment line terminated by a semicolon.

always
begin
statement
.... end