AMD supports byte write enable in block RAM. Use byte write enable in block RAM to:
- Exercise advanced control over writing data into RAM
- Separately specify the writeable portions of 8 bits of an addressed memory
From the standpoint of HDL modeling and inference, the concept is best described as a column-based write:
- The RAM is seen as a collection of equal size columns
- During a write cycle, you separately control writing into each of these columns
Vivado synthesis inference lets you take advantage of the block RAM byte write enable feature. The described RAM is implemented on block RAM resources, using the byte write enable capability, provided that the following requirements are met:
- Write columns of equal widths
- Allowed write column widths: 8-bit, 9-bit, 16-bit, 18-bit (multiple of 8-bit or 9-bit)
For other write column widths, such as 5-bit or 12-bit (non multiple of 8-bit or 9-bit), Vivado synthesis uses separate RAMs for each column:
- Number of write columns: any
- Supported read-write synchronizations: read-first, write-first, no-change