When defining a port, the port:
- Can be constrained or unconstrained.
- Are usually constrained.
- Can be left unconstrained in the entity declaration.
- If ports are left unconstrained, their width is defined at instantiation when the connection is made between formal ports and actual signals.
- Unconstrained ports allow you to create different instantiations of the same entity, defining different port widths.
Recommended: Do not use unconstrained ports. Define ports
that are constrained through generics. Apply different values of those generics at
instantiation. Do not have an unconstrained port on the top-level entity.
Array types of more than one-dimension are not accepted as ports. The entity declaration can also declare VHDL generics.