Example with Custom Attribute on a Signal (Verilog)

Example with Custom Attribute on a Signal (Verilog) - 2023.2 English

Vivado Design Suite User Guide: Synthesis (UG901)

Document ID

UG901

Release Date

2023-11-01

Version

2023.2 English

(* my_att = "my_value", DONT_TOUCH = "yes" *) reg my_signal;