Vivado synthesis supports behavioral Verilog legal statements.
- The following statements (variable and signal assignments) are legal:
- variable = expression
- if (condition) statement
- else statement
- case (expression), for
example:
expression: statement ... default: statement endcase - for (variable = expression; condition; variable = variable + expression) statement
- while (condition) statement
- forever statement
- functions and tasks
- All variables are declared as integer or reg.
- A variable cannot be declared as a wire.