VHDL Predefined IEEE Real Type and IEEE Math_Real Packages

VHDL Predefined IEEE Real Type and IEEE Math_Real Packages - 2023.2 English

Vivado Design Suite User Guide: Synthesis (UG901)

Document ID

UG901

Release Date

2023-11-01

Version

2023.2 English

VHDL predefined IEEE real type and IEEE math_real packages are supported only for calculations such as the calculation of generics values, and cannot be used to describe synthesizable functionality.