After you have a synthesized netlist, you can load it into memory together with the XDC files or Tcl scripts enabled for implementation. You must review the messages issued by the tool when loading the XDC in order to verify and correct any constraint that cannot be applied.
In some cases, the object names in the synthesized netlist are different from the names in the elaborated design. If this is the case, you must recreate some constraints with the corrected names, and save them in an implementation-only XDC file.
After the tool can properly load all the XDC files, you can run timing analysis in order to:
- Add missing constraints, such as input and output delay.
- Add timing exceptions, such as false paths, multicycle paths, and min/max delay constraints.
- Identify large violations due to long paths in the design and correct the RTL description.
You can use the same base constraints as during synthesis, and create a second XDC file to store all new constraints specific to implementation. You can choose to save physical and configuration constraints in a separate XDC file.
The netlist-based XDC iteration is shown in Figure 1.