The Timing Constraints wizard analyzes the feedback loop connectivity of the MMCM and PLL
cells present in the design. External delay constraints (min and max) are recommended
CLKFBOUT pins are connected to
the design ports through IO buffers and the MMCM or PLL property COMPENSATION=EXTERNAL.
The following figure illustrates the recommended External Delay constraints.
The following figure illustrates a typical MMCM with external feedback path circuit.
In the current Vivado Design Suite release, the Timing Constraints wizard cannot recommend external delay constraints when there is a sequential cell in the feedback path, such as ODDR, which is used for generating a forwarded clock. In this case, you must create the external delay constraints manually or using the Timing Constraints window after exiting the wizard.