I/O constraints configure:
- Cells connected to ports Typical constraints include:
- I/O standard
- I/O location
The Vivado Design Suite supports many of the same I/O constraints as the Integrated Software Environment (ISE) Design Suite. The following list of I/O properties is not exhaustive.
- For a complete list of I/O properties, more information on I/O port and I/O cell
properties, and coding examples with proper syntax, see the
Design Suite Properties Reference Guide (UG912).Note: All properties are applied to port objects unless otherwise stated.
- For more information on the application and methodology behind these properties, see the device SelectIO™ documents, for example 7 Series FPGAs SelectIO Resources User Guide (UG471).
- Sets the output buffer drive strength (in mA), available with certain I/O standards only.
- Sets an I/O Standard.
- Sets the slew rate (the rate of transition) behavior of a device output.
- Sets the configuration of the input termination resistance for an input port.
- Turns on or off the 100 ohm differential termination for primitives such as
- Applies a weak driver on an tri-stateable output or bidirectional port to preserve its value when not being driven.
- Applies a weak logic low or high level on a tri-stateable output or bidirectional port to prevent it from floating.
- Defines a set of master and slave banks. The DCI reference voltage is chained from the master bank to the slaves. DCI_CASACDE is set on IOBANK objects.
- Frees the Vref pins of an I/O Bank and uses an internally generated Vref instead. INTERNAL_VREF is set on IOBANK objects
- Groups a set of IDELAY and IODELAY cells with an IDELAYCTRL to enable automatic replication and placement of IDELAYCTRL in a design.
- Tells the placer to try to place FFs in I/O Logic instead of the fabric slice.
This property must be assigned to the register and not to the port.Important: There are notable differences between the ISE Design Suite and the Vivado Design Suite in the handling of IOB. The Vivado tools allow IOB to be set on both ports and on register cells connected to ports. If conflicting values are set on a port and its register, the value on the register prevails. The Vivado tools use only the values TRUE and FALSE. The value FORCE is interpreted as TRUE, and the value AUTO is ignored. Unlike ISE, if a setting of IOB true cannot be honored, the Vivado tools generate a critical warning, not an error.
- For HDIO in AMD UltraScale+™ devices. Tells the placer to try to place FFs driving Tristate signals on HDIO bank IOBs in the I/O Logic instead of the fabric slice. This property must be assigned to the register and not to the port.