set_output_delay command specifies the output path delay of an
output port relative to a clock edge at the interface of the design.
Video: For training on output delay, see the Vivado Design Suite QuickTake Video: Setting Output Delay.
When considering the application board, this delay represents the phase difference between:
- The data propagating from the output package pin of the FPGA, through the board to another device, and
- The relative reference board clock.
The output delay value can be positive or negative, depending on the clock and data relative phase outside the FPGA.
Note: Output delays can also be set on internal data pins such as, STARTUPE3/DATA_OUT[0:3] (UltraScale+ devices).