The AMD Vivado™ Design Suite enables implementation of the following AMD device architectures: AMD Versal™ adaptive compute acceleration platform (adaptive SoC), AMD UltraScale™ , AMD UltraScale+™ , and AMD 7 series FPGA. A variety of design sources are supported, including:
- RTL designs
- Netlist designs
- IP-centric design flows
The Figure 1 shows the Vivado tools flow.
Vivado implementation includes all steps necessary to place and route the netlist onto device resources, within the logical, physical, and timing constraints of the design.
For more information about the design flows supported by the Vivado tools, see the Vivado Design Suite User Guide: Design Flows Overview (UG892).