Property Based Logic Optimization - 2023.2 English

Vivado Design Suite User Guide: Implementation (UG904)

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2023.2 English

Certain optimizations can be performed on specific objects rather than the entire design. These optimizations are triggered by object properties. Logic Optimization detects the presence of these properties and automatically runs the necessary optimization phases.

This is true for all properties except for shift register optimizations properties, which require the -shift_register_opt option. The following is a summary of properties for object-specific optimization.

Table 1. Logic Optimization Properties
Property Description
MUXF_REMAP Set to TRUE on MUXF primitives to convert them to LUTs
CARRY_REMAP Set the threshold on CARRY primitives to convert to LUTs
SRL_TO_REG 1 Set to TRUE on SRL primitives to convert them to register chains
REG_TO_SRL 1 Set to TRUE on register chains to convert them to SRL primitives
SRL_STAGES_TO_REG_INPUT 1 Set to the appropriate value on an SRL primitive to move a register across its input
SRL_STAGES_TO_REG_OUTPUT 1 Set to the appropriate value on an SRL primitive to move a register across its output
LUT_REMAP Set to TRUE on cascaded LUTs to reduce LUT levels
CONTROL_SET_REMAP Set on registers to specify the type of control signal to remap to LUTs
EQUIVALENT_DRIVER_OPT Set on logically-equivalent drivers to force or prevent merging
CLOCK_BUFFER_TYPE Set on nets to insert corresponding Global Clock buffers
LUT_DECOMPOSE Set on LUTs (LUT5, LUT6) for decomposition to reduce congestion
  1. Requires -shift_register_opt option to perform optimization.