This section reports a few known issues with the current release for Hierarchical Design flows.
Limitations on Global Clock Routing
Clocks driven by a buffer in the top level will not be routed during the OOC implementation. Routing estimations will be used, and the use of HD.CLK_SRC will help improve routing estimates. Clock buffers within the OOC module will be routed during OOC implementation. With proper constraints on the OOC clocks, this timing estimation is sufficient to give accurate results for timing.
Limitations on OOC Module with IDELAYCTRL
An OOC module with IDELAYCTRL can be imported, but not locked. Therefore, the OOC module will not be preserved 100%.
No Project Mode Support
There is currently no project mode support for Hierarchical Design in the Vivado Design Suite.