To process a design using the Module Analysis flow, none of the following constraints are absolutely required. For more accurate timing analysis, use of HD.CLK_SRC and create_clock are strongly encouraged. All other constraints are optional.
When using a Module Reuse flow, these context constraints become much more important. For successful assembly of designs with OOC modules, these constraints ensure that the physical resources are appropriately allocated, clock interactions are understood, and information about the module interfaces are accurately set. Without establishing the constraints for each module, assembly become more difficult.