In AMD
7 series devices, if
block RAMs are found to be cascaded, because only one block RAM can be active at any
time, the rest of the block RAMs can be disabled based on address and any existing
enable conditions. This enables large power savings. These optimizations are
performed by default in the opt_design phase in the
AMD Vivado™ Design Suite.
Versal block RAM Power Optimization only includes the two type of
optimizations:
- Write Mode Optimization
- Change the WRITE_MODE to NO_CHANGE if the output is not consumed on the following clock cycle.
- Structural Optimization
- Swap the EN and WE on write-only ports to reduce enable time.