Power Analysis of SD-FEC Core - 2023.2 English

Vivado Design Suite User Guide: Power Analysis and Optimization (UG907)

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2023.2 English
Report Power supports the power analysis of Soft-Decision FEC core available in AMD Zynq™ UltraScale+™ RFSoCs. When the design containing the SD-FEC IP is implemented, Report Power displays the power analysis as shown in the following figure.
Figure 1. Report Power with SD-FEC Power Analysis

Following properties can be modified before running the Report Power for the SD-FEC object after implementation:

  • LD_PERCENT_LOAD: Percentage utilization for LDPC Decoder core
  • LE_PERCENT_LOAD: Percentage utilization for LDPC Encoder core
  • TD_PERCENT_LOAD: Percentage utilization for Turbo Decoder core

These three properties can also be provided during SD-FEC IP customization and using set_property commands on an implemented design. Also, the generated .xpe file by Report Power command can be imported to XPE spreadsheet for further what-if analysis.