# Power Terminology - 2023.2 English

## Vivado Design Suite User Guide: Power Analysis and Optimization (UG907)

Document ID
UG907
Release Date
2023-10-18
Version
2023.2 English

The following terminology is used in this guide.

Power Estimation
Power estimation is the process of calculating design power before the design implementation begins. Estimated device resource totals and activity rates are entered into a power estimation tool such as Xilinx Power Estimator or Power Design Manager to get the estimated device power.
Power Analysis
Power analysis is the calculation of design power throughout design implementation. Power analysis uses the design netlist, which becomes available after the RTL synthesis step. After the design is fully routed, power analysis uses the exact device resources and routing interconnect along with propagated switching activity to calculate design power for the most accurate result.
Device Static Power
Device static power is the power from transistor leakage on all connected voltage rails and the circuits required for the device to operate normally, post configuration. This is normally measured by programing a blank bitstream into the device. Device static power is a function of process, voltage, and temperature. This represents the steady state, intrinsic leakage in the device.
Design Power
Design power is the dynamic power of the user design, due to the input data pattern and the design internal activity. This power is instantaneous and varies at each clock cycle. It depends on voltage levels, logic, and routing resources used. This also includes static current from I/O terminations, clock managers, and other circuits that need power when used. It does not include power supplied to off-chip devices.
Total On-Chip Power
Total on-chip power is the power consumed internally within the device, equal to the sum of device static power and design power. It is also known as thermal power.
Off-Chip Power
Off-chip power is the current that flows from the supply source through the device power pins, then out of the I/Os and dissipated in external board components. The currents supplied by the device are generally consumed in off-chip components such as I/O terminations, LEDs, or the I/O buffers of other chips, and therefore do not raise the device junction temperature.
Note: Negative off-chip power dissipated is the power that is sourced from external source and dissipated inside our device.
Power-On Current
Power-on current is transient current that occurs when power is first applied to the device. This current varies for each voltage supply and depends on the device construction as well as the ability of the power supply source to ramp up to the nominal voltage. This current also depends on the device's operating conditions, such as temperature and sequencing between the different supplies. Power-on current is generally lower than operating current due to architectural enhancements as well as adherence to proper power-on sequencing.
Ambient Temperature (°C)
Ambient temperature is the temperature of the air immediately surrounding the device under the expected system operating conditions.
Effective Thermal Resistance to Air (ΘJA (°C/W))
Effective thermal resistance to air is also known as Theta-JA and ΘJA. This coefficient defines how power is dissipated from the device silicon to the environment (device junction to ambient air). It includes contributions from all elements, from the silicon chip dimensions to the surrounding air, plus any material in between, such as the package, the PCB, any heat sink, and airflow. Typically this combines thermal resistance and interdependencies from the two main paths by which the generated heat can escape onto the environment:
• Upward from the die to the air (junction to air or ΘJA).
• Downward from the die through the board and into the air (junction to board or ΘJB).

For detailed information on thermal resistance, refer to 7 Series FPGAs Packaging and Pinout Product Specification (UG475), UltraScale and UltraScale+ FPGAs Packaging and Pinouts Product Specification (UG575) and for thermal resistance in Versal devices, refer to Versal Adaptive SoC Packaging and Pinouts Architecture Manual (AM013).

Important: The thermal data mentioned in this user guide is for the device/package comparison only. Do not use these values for thermal simulations design. Use the thermal models provided on Xilinx.com.