Vectorless Power Analysis - 2023.2 English

Vivado Design Suite User Guide: Power Analysis and Optimization (UG907)

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2023.2 English

The vectorless propagation engine predicts switching activity of design nodes where no activity is specified by design constraints or no activity is provided from simulation results. The vectorless engine assigns initial seeds (default signal rates and static probability) to all undefined nodes. Then, starting from the design primary inputs it propagates activity to the output of internal nodes, and repeats this operation until the primary outputs are reached. The algorithm understands the design connectivity and resource functionality and configuration. Its heuristics can even approximate the glitching rate for any nodes in the netlist. Glitching occurs when design elements change states multiple times in between active clock edges before settling to a final value. The vectorless propagation engine is not as accurate as a post-route simulation with a reasonably long duration and realistic stimulus, but it is an excellent compromise between accuracy and compute efficiency.

Important: The vectorless Xilinx Power Estimator does not propagate activity to the output ports of GTs. If any design logic depends on these activity rates, you must explicitly specify the activity rates on GT outputs using set_switching_activity -type <rx_data|tx_data> commands to achieve an accurate analysis.

The vectorless power analysis is an average power estimation for the design, unless you have specifically overridden switching rates and static probability for the design.

Power Constraints to Improve Vectorless Analysis

In any design, the activity of specific nodes are imposed by the system specification or the interfaces with which the device communicates. Providing this information as power constraints to the tools, especially for high-fanout control signals like resets, clock enables, and clocks, will help guide the power estimation algorithms. These nodes include:

Clock Activity
Timing constraints specify the exact frequency of all device clock domains, whether externally provided (input ports), internally generated, or externally supplied to the printed circuit board (output ports). The design should have at least one clock specified using the create_clock constraint. If no clock is defined, then Report Power issues a warning message and uses a 10 GHz clock frequency for switching activity computations.
I/O Data Ports
With your knowledge of the exact protocols and format of the data flowing in and out of the device, you can specify signal transition rate or signal static probability rate in the tools for at least some of the I/Os. For example, some protocols have a DC balanced requirement (signal static probability rate = 50%) or you can know how often data is written or read from your memory interface, so you can set the data rate of strobe and data signals. If no user activity rate is specified on primary inputs, Report Power assigns a default static probability of 0.5 and a default toggle rate of 12.5%.
I/O and Internal Control Signals
With your knowledge of the system and the expected functionality you can predict the activity on control signals such as Set, Reset and Clock Enable. These signals typically can turn on or off large pieces of the design logic, so providing this activity information increases the power estimation accuracy. If a primary input is found to be reset (that is, directly connected to the RESET pin of sequential elements), then the tool assigns a default static probability of 0 and a default signal rate of 0. Similarly, if a primary input is found to be Clock Enable (that is, directly connected to the CE pin of sequential elements), then the tool assigns a default static probability of 0.99 and a default signal rate of 2.