To use the AMD Vivado™ debug cores, the design must contain an AXI4 Debug Hub. The AXI4 Debug Hub connects an AXI4 interface of the CIPS with the AXI4-Stream interface. The interface connects to Vivado debug cores, which includes the following types of cores:
- AXI4-Stream Integrated Logic Analyzer (AXIS-ILA)
- AXI4-Stream Virtual Input/Output (AXIS-VIO)
- PCI Express® Link Debugger
|AXI4 Debug Hub Connectivity
|Automatic AXI4 Debug Hub post-synthesis netlist insertion and connection.
|This method is recommended for most use cases as it provides the most
Note: This method cannot be used on designs that use Dynamic Function eXchange (DFX).
|Manual AXI4 Debug Hub instantiation, automatic post-synthesis netlist debug core connection.
|This method should be used when it is desired to manually assign the
address used by the AXI4 Debug Hub
or when Dynamic Function eXchange (DFX) is used. In this case the design
should have a manually instantiated AXI4 Debug Hub with a connection to an AXI4 master from the Control, Interface,
and Processing (CIPS) IP.
|Manual AXI4 Debug Hub instantiation, manual debug core connection.
|This method should be used when it is desired to manually define all
connectivity between the AXI4 Debug
Hub, CIPS, and all debug cores in the design. This method can also be
used when the design uses Dynamic Function eXchange (DFX).