To clear the AES key manually, disconnect the Vbatt pins and power-cycle the board.
Note: Pressing or pulsing the PROG pin when the board/FPGA is powered up will not clear the BBR register.
Alternatively, you can clear the AES key in Vivado IDE by right-clicking the FPGA device in the Hardware window, selecting Clear BBR Key
Figure 1. Clearing the AES Key for 7 Series Devices
When the Clear BBR Key dialog box appears, click OK to clear the key from the device
Figure 2. Clear BBR Key Dialog Box
verify_hw_devicesis performed on the BBR key, an error will be shown. To verify the BBR key, the user should test this by programming the FPGA with a bitstream that has the key. Vivado does not support any post BBR program verify option to verify the programmed BBR key.