Programming an FPGA or ACAP prior to debugging involves exactly the same steps described in Programming the FPGA or ACAP. After programming the device with the .pdi file that contains the IBERT core, the Hardware window now shows the components of the IBERT core with the RTL instance name shown in parenthesis, that were detected when scanning the device (see the following figure).
Important: In designs using the In-System IBERT IP for UltraScale and UltraScale+ designs, you will see the In-System IBERT core being detected in the Hardware window.
Figure 1. Hardware Window Showing the IBERT Core