Open the synthesized design by clicking Open Synthesized Design in the Flow Navigator and select the Debug window layout to see the Debug window. Any nets that correspond to HDL signals that were marked for debugging are shown in the Unassigned Debug Nets folder in the Debug window.
Figure 1. Unassigned Debug Nets
- Selecting a net in any of the design views (such as Netlist or Schematic windows), right-click select the Mark Debug option.
- Selecting a net in any design views, drag, and drop the nets into the Unassigned Debug Nets folder.
- Using the net selector in the Set up Debug wizard (see Using the Set Up Debug Wizard to Insert Debug Cores for details).