The design can be functionally debugged during the simulation verification process. AMD provides a full design simulation feature in the AMD Vivado™ IDE. The AMD Vivado™ design simulator can be used to perform RTL simulation of your design. The benefits of debugging your design in an RTL-level simulation environment include full visibility of the entire design and ability to quickly iterate through the design/debug cycle. The limitations of debugging your design using RTL-level simulation includes the difficulty of simulating larger designs in a reasonable amount of time in addition to the difficulty of accurately simulating the actual system environment. For more information about using the AMD Vivado™ simulator, refer to the Vivado Design Suite User Guide: Logic Simulation (UG900).